Re: [SI-LIST] : Embedded Capacitance Project

From: [email protected]
Date: Fri Dec 17 1999 - 15:50:28 PST

• Next message: Ron Miller: "Re: [SI-LIST] : Inner vs. Outer Layer Routing"
• Previous message: Jim Freeman: "Re: [SI-LIST] : Physcially-small far-end LVDS terminations?"
• Maybe in reply to: Grasso, Charles (Chaz): "[SI-LIST] : Embedded Capacitance Project"

Tony:

Embedded capacitance normally demands very small dielectric thicknesses (~2
mils of FR-4 for Hadco ZBC2000); therefore, the fringing capacitance effects
are minimal. This results in a very close correlation to the ideal
capacitance one computes from the standard A*Er*Eo/D equation. If you
deplete the capacitive plate area with antipads, the capacitance reduction is
directly proportional to the percentage reduction in plate area.

Hope this helps,

Michael L. Conn
Owner/Principal Consultant
Mikon Consulting

*** Serving Your Needs with Technical Excellence ***

**** To unsubscribe from si-list: send e-mail to [email protected]. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list
****

• Next message: Ron Miller: "Re: [SI-LIST] : Inner vs. Outer Layer Routing"
• Previous message: Jim Freeman: "Re: [SI-LIST] : Physcially-small far-end LVDS terminations?"
• Maybe in reply to: Grasso, Charles (Chaz): "[SI-LIST] : Embedded Capacitance Project"

This archive was generated by hypermail 2b29 : Tue Feb 29 2000 - 11:39:09 PST