EXPERIMENTAL DIRECT DIGITAL SYNTHESIS
BASED ON A MICROCONTROLLER AND
PHASE LOCKED LOOP
(2003)

THIS VERSION IS REPLACED BY AN IMPROVED VERSION WITH BETTER PLL SYSTEM
CLICK HERE FOR THIS IMPROVED VERSION


The Microcontroller DDS with PLL from 7 to 30 MHz and the
original DDS of Ton, PA0KLT with rotary encoder in a test setup.

DDS with a microcontroller
In the Benelux QRP club magazine nr. 103 (September 2002) was an article from Ton, PA0KLT about a QRP tuning system. The system works with a DDS made with a microcontroller! Another device (counter or other microcontroller) is used to display the frequency.

Frequency read out added to the microcontroller DDS circuit
In my version I added a simple one 7 segments display as a frequency display. So the usual combination of a DDS chip with a microcontroller to control the DDS is now reduced to just one microcontroller. This microcontroller works as a DDS, it displays the frequency on a 7 segments display and it reacts on pressing the 3 tuning buttons.

NOTE: The disadvantage of using only 7 bits and the low clock frequency of 923 kHz is that there are some spurs and glitches but that is no problem, they are efficiently suppressed in the PLL loop filter! The quality of the loop filter is important for a good result.
As they are all within the audio band, they never cause any reception of unwanted signals as is the case with a "normal" DDS. In practice and after optimizing the loop filter, I never found such spurious while listening to the amateur bands.


The DDS with microcontroller and display.
Output frequency 5859 Hz to 29297 Hz (RF frequency 6 to 30 MHz).
big diagram

The DDS Microcontroller
The heart of the DDS is the fast but simple and cheap microcontroller AT90S1200. The crystal frequency is 11999.55 MHz so a 12 MHz crystal can be used. The DDS controls a VCO with a frequency of 6 to 30 MHz. The frequency of this VCO is divided by 1024 and locked to the DDS with a phase locked loop circuit. The frequency range of the DDS is then 5859 to 29297 Hz.
One loop is 13 machine cycli so the clock frequency of the DDS is 11999.55 / 13 = 923.04 kHz. The output form is not a sine but a triangle. The output port D, bits 0 to 6, is together with the resistor network, the simple 7 bits D/A converter.
Ports B1, B2, B3, B4 are also used as inputs. In that case, the LED display is switched off by the BC557 transistor.


Tuning is done with 3 switches, two for tuning, one for the tuning speed.
I took an old mouse for it, only the 3 switches are used.
An extra switch is added as it was a two-button mouse.

Tuning of the DDS
Tuning of the DDS is done by 3 switches of an old 3 button mouse (only the switches are used) and works very pleasant. Two buttons are for tuning the frequency up or down, the third one is for the tuning speed. There are 6 tuning speeds of the final VCO (that works at a 1024x higher frequency): 15.625 Hz, 31.25 Hz, 125 Hz, 1 kHz, 10 kHz and 100 kHz. Pushing the speed button will change the speed, it is displayed on the 7 segments LED display. When pushing the frequency up or down button, 9.1 of such frequency steps per second are executed.
When executing a frequency step, the DDS runs 9.1x per second at 1/8 of the normal clock speed of 923 kHz. The same applies for when the frequency display is active. There is an extra switch to switch off the frequency display so that you will have a real clean VFO signal.


How can you read the frequency with only one display?
Very simple if you know it!

Frequency display
For the 3 lower tuning speeds, the kHz value of the frequency is displayed.
When the 10 kHz or 100 kHz tuning speed is selected, the MHz + 100 kHz value of the frequency is displayed.
That works as follows:

For a frequency of 21.345 MHz and 10 kHz - 100 kHz tuning speed:
Display "2" during 0.2 second
Display off during 0.1 second
Display "1" during 0.2 second
Display off during 0.1 second
Display "3" during 0.2 second
Then the display is off during 2 seconds and the frequency is displayed again.

For a frequency of 21.345 MHz and one of the lower tuning speeds selected:
Display "3" during 0.2 second
Display off during 0.1 second
Display "4" during 0.2 second
Display off during 0.1 second
Display "5" during 0.2 second
Then the display is off during 2 second and the frequency is displayed again.

The display is off during 2 seconds but the frequency is displayed immediately after the frequency up-down buttons are released.

Switch on the display when you want to read the frequency. Switch it off after tuning for a really stable and clean VFO signal.

When the speed button is pressed, the speed (0 to 5) is displayed. It steps slowly (0.5 seconds per step), just release the button at the desired speed.


The VCO with output driver and /1024 divider.
big diagram

The VCO with output driver and /1024 divider
What can I say about it, just a VCO with a transistor and a switch for the two frequency ranges. The VCO is buffered with a 74HCU04 (perhaps a 74HC04 can be used) and the 74HC4060 divides the VCO frequency by 1024. This signal goes to the PLL circuit. Simple indeed!


The phase locked loop circuit with extra loop filter to reduce the spurious signals.
This circuit can be replaced by the new phase-frequency detector circuit described below.
big diagram

Phase locked loop
This is not the usual circuit with a phase-frequency detector with set-reset flip flops or a dedicated PLL chip. The 3 input transistor do buffer and filter the triangle DDS signal. The output of this filter / buffer is a sine wave. This signal is sampled by two samplers. The (VCO signal/1024) controls the sampler. One sampler is active at the positive edge of the (VCO signal/1024) and the DDS signal, the other at the negative edges of both signals. So the PLL controls the VCO at twice the DDS frequency instead of only once as is the case with a standard PLL system. It also prevents locking on half the frequency (for example 14 MHz if 28 MHz is selected).

The short sample pulse for the two 74HC4066 switches is generated by the 220 pF / 4700 ohm networks. Two switches are connected in parallel to lower the resistance of the switches. During the sample pulse, the 10 nF capacitors is charged to the momentary value of the DDS signal and that is a measure of the phase between the DDS and the (VCO signal/1024).
Both signals are added (one inverted first) and the VCO is controlled via the 120 k ohm resistor. The 100 uF capacitor with the 120 ohm series resistor RL are the loop filter. If instable, play a little with the value of RL.

When unlocked, the samplers will generate random values. If these values differ more than 0.7 V (one B-E junction) from the 100 uF capacitor voltage, the transistors will become active and control the VCO till there is a lock again. This is a process that depends on random samples from the samplers, but locking will occur within 0.1 s.

The potentiometer is adjusted for a correct locking. Set the DDS to the highest frequency (30 MHz) and discharge the 100 uF capacitor by shortening it for a moment. Check if the PLL locks to 30 MHz. If not, readjust the potentiometer.

Optimized loop filter
The 27k resistor and the 0.1 uF capacitor are an extra loop filter to reduce the spurious audio signals effectively. Do not take a too high R and C value, then the loop will start to oscillate with a frequency of a few Herz.


Interior of the DDS with PLL and VCO.


Example with a bad loop filter near 19691 kHz
(1024 x 923 kHz DDS clock frequency / 48).
And how it is effectively suppressed
by an optimized loop filter!
Software for the AT90S1200
The crystal frequency is 11999.55 kHz. One loop of the DDS routine is 13 cycles, giving a clock frequency of 923.04225 kHz.
The DDS Accumulator Register is 4 bytes long: 256*256*256*256 = 4294967296. The Frequency Tuning Word is also 4 bytes.
The output frequency of the DDS is (923.04225 kHz * Frequency Tuning Word) / 4294967296, the PLL frequency is 1024x higher
The value of the Frequency Tuning Word is changed by pressing the up-down buttons.

The trick is that changing the Frequency Tuning Word with a value of 4544 causes a frequency change of exactly 1 kHz and that 4544 is 64x71. The smallest step used is therefore 71, giving 15.625 Hz frequency variation.
If the Frequency Tuning Word is changed, the decimal digits of the display are changed accordingly. There is one register reserved for each decimal digit of the frequency. However, the lowest byte of that register is not a 0 to 9 counter but a 0 to 64 counter. If the lowest byte exceeds 63 or is lower than 0, all other decimal values are adjusted.
This method was designed as all routines have to be an exact number of machine cycles, independent of what is happening. If a button is pressed, the DDS clock is 1/8 of its normal clock speed of 923 kHz and the Frequency Tuning Word is multiplied by 8.
However, it was very difficult to count all the machine cycles exactly so in the end I corrected the exact length of the various routines by listening to the output signal with a receiver and corrected various delays for best performance.
As the performance is not as good as when at full clock speed, the display can be switched off for best results.

A frequency offset is programmed by setting different initial values to the Frequency Tuning Word and the decimal digit registers.

Click to Download the Software for the AT90S1200: "03dds1soft.zip" with the .asm files needed to program the AT90S1200

Results
The DDS PLL is used as VFO for a simple Direct Conversion receiver that is connected to the Soundcard of the PC. It is possible to decode various digital signals with free available PC programs, there are very nice DSP programs for filtering the wide band audio signal.
But most of the time this receiver is used in wide band audio mode: All signals from -8 to +8 kHz around the tuned frequency can be heard as background sound in the shack during home brewing or when using the computer.
Performance is good, it is very funny to hear al the signals in such a wide band instead of only one in a narrow band as is the case when making a QSO. In practice, there are no problems with spurious signals and glitches.

The original DDS of Ton, PA0KLT
The original DDS of Ton, PA0KLT has a D/A converter with 8 bits and a sine output, the clock frequency is higher and another PLL system is used. Tuning is done with a comfortable rotary encoder instead of 3 pushbuttons and he has implemented features to set the minimum and maximum frequency, it has a frequency memory and the tuning speeds are fully programmable. The microcontroller in his DDS is an AT90S2313 with more capabilities than the AT90S1200 in my DDS.
Another advantage is that his DDS runs at half the clock speed during tuning. Mine at 1/8 of the clock speed during tuning. At 28 MHz you can hear that during tuning of my DDS but the DDS of Ton has a perfect silent tuning.
Using a microcontroller as a DDS is a very interesting idea, good for a lot of experiments in the future.

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