The Dutch D-ATV Project

We have developed a DVB-S modulator in a single FPGA which can be used for digital amateur television transmissions. On this page you find some present and historical information which involves our D-ATV design.

29 Nov 2004: The D-ATV transmitter board set is currently sold out. Contact us for more information.

30 Oct 2004: We have implemented a new feature which now enables the transmission of Teletext in one or both streams. Also a new version of DVB Config is developed. The new DVB Config 2005 supports editing and uploading of Teletext pages into the D-ATV board.

20 Oct 2004: Boards are available now. Contact us for ordering information.

18 Oct 2003: Currently we have started the production of a first small batch of our DVB modulator. More info will follow.

12 July 2003: At this time we are working on a cheap version of our fully working DVB-S transmitter. The IQ modulator boards for 13cm and 23cm are ready and tested. We are using the direct conversion technique for generation of the QPSK spectrum. This technique requires careful PCB design in order to minimize unwanted feedback of the modulated output back to the input of the IQ modulator. This is much harder to achieve at 13cm than for 23cm due to practical RF aspects like undesired feedback and coupling, shielding etc. Therefore when we had to decide which design to complete first we chose for the more difficult 13cm version. Now we also have our 23cm board working and the results look great. We done some an EVM test which shows values of approximately 750m% EVM for the 23cm edition which is really good.

We decided to make seperate designs for 13cm and 23cm in order to achieve maximum performance for both frequency bands. This means that we payed more attention in achieving low phase noise for our custom VCO designs. With our VCO design for 13cm we achieve a typical phasenoise level of -87dBc/Hz @10 kHz distance of the carrier. For 23cm this value becomes even better with typical -92 dBc/Hz @ 10 kHz offset. The commercial version of the FPGA board has been assembled and works great too. The results of the measurements on the 13cm IQ modulator board are given below. The vector signal analysis result shows that the EVM is approximately 1.6%. This value is caused by a slight IQ imbalance (small mismatch between I and Q amplitude levels). This slight mismatch will not be an issue in practice (you need a €100.000 measurement device to detect these imperfections !).

Some additional features are being programmed now. The board supports 2 MPEG Transport streams, multiple symbolrate settings, all FEC ratios and more.

08-August-2002: First Dutch D-ATV field trials succeeded !!

Currently the Dutch D-ATV team is developing it's own Digital ATV transmitter according to the DVB-S standard. This project spans several toimages which includes digital and RF aspects. We have designed all major DVB signal processing blocks in VHDL and have put all these blocks together now. We have done some first field trail tests with complete D-ATV transmitter test setups and live MPEG2 pictures from our cameras. For us this major breakthrough is again celebrated with a bottle of:

Both Werner (PE1OBW) and Henk (PE1JOK) have done some first field trials with several local radio amateurs. Werner's setup consisted of a experimental 23cm upconverter unit. He has done some tests to Almere with 1 Watt output (approx. 20 km to PE1PZN), Landsmeer with 130mW (15km) and Nieuwegein with 5W (30km ). All tests worked out succesfully. Some screenshots are displayed below.

Figure 1. Screen shot of the received D-ATV transmission from PE1OBW to PE1PZN on his Nokia 9500

Figure 2. Received D-ATV transmission from PE1OBW, Willem PE1PCF in shack.

Figure 3. Screen shot of the received D-ATV transmission from PE1OBW distorted by radar.

Beside Werner's tests also Henk (PE1JOK) worked his first D-ATV contact over a distance of approx. 30km with Sjaak (PE1HLR) at the 7th of August 2002. The test setup consisted of the experimental FPGA development board whichs holds the DVB core, our Philips MPEG encoder board and a transmitter setup with analog I/Q modulator and some power amplifiers. Sjaak received the signal with a Humax IRCI 5400 at a frequency of 1270 MHz. Symbolrate was set to 6,25 Msym/s and FEC adjusted to 1/2 rate. Fortunately Sjaak took some photographs of his TV screen:


Figure 4. Screen shot of the received D-ATV tranmission from PE1JOK to PE1HLR


Figure 5. Another screen capture of the first D-ATV field trial from PE1JOK as received on PE1HLR's Humax

Initial transmitted power had been set at 2 Watt. Later we did some tests with 10dB less power which still resulted in B5 pictures!

Figure 6. Received signal strength indication and signal quality indication of the FEC. Btw RF Freq = 11870 - 10600=1270 Mhz.

More technical details on our project is described below.

02-May-2002: Status of Project

Digital Baseband Processing :

DVB-S PRBS Data Scrambler : fully written in VHDL. Status ready.

Reed Solomon Encoder(188,204) : fully written in VHDL. Status ready.

Convolutional Interleaver : fully written in VHDL. Status ready.

Convolutional Encoder 1/2 rate: fully written in VHDL. Status ready.

Puncturing : fully written in VHDL. Status ready.

Root Raised Cosine Filtering : fully written in VHDL. Status ready.

Our first test setups have been done with some very experimental upconversion breadboards which put us in the position to do some measurements on DVB-S settop boxes like the Nokia-9500 and Humax IRCI5400. Besides that we are in the comfortable position to do some extra nice tests with a DVB-S demodulator demoboard (OM5718) which we obtained from our dear friends at the Philips Natlab Netherlands. Our great thanks for that go to Oswald Moonen, Peter Rutten (PA3CEZ) and Stefan Crijns from the Philips Semiconductor group who supported us with this measurement tool especially for our DVB project. The OM5718 demoboard is a special development demoboard for the TDA8044 DVB-S demodulator chip which was developed by people from the above mentioned Philips department in the Netherlands.The TDA8044 DVB-S demodulator chip is used in the well known Humax IRCI5400 STB.
Below are some screenshots of the OM5718 demoboard software which shows the results of the measurements on our working DVB-core. Symbolrate during these measurements has been set to 6.25 MSym/s and FEC rate 5/6.

Figure 7. Screen capture from OM5718 Philips DVB-S demodulator software which shows that our DVB-S core works.

As can be seen in above picture is a full FEC lock which shows that our complete Forward Error Correction is working correctly. In the picture below an additional screenshot shows the estimated bit error rate performance as predicted by the TDA8044 chip.

Figure 8. Screen capture from OM5718 Philips DVB-S demodulator software which estimates Bit Error Rate perfomance.

Finally we did some measurements with the Agilent VSA89600 Vector Signal Analyzer which shows the very clean frequency spectrum output which of course is dependant to the performance of our digital FIR filters and furthermore shows the nice constellation diagram and Error Vector Magnitude (EVM).

Figure 9. Vector Signal Analysis measurement on our first working DVB-S core. Output spectrum at 60 MHz IF, Constellation and low EVM.

RF Processing :

Several modulator chips have been evaluated. Currently one topology is already elaborated on a first version Printed Circuit Board. Status: ready (02-May-2002).

MPEG2 Encoding :

We have evaluated several MPEG2 encoder chips for price/performance and availability. Some MPEG2 tests have been done with a direct interface to the MPEG2 decoders of the following commercial DVB-S receivers:

- Nokia 9500
- Humax IRCI5400

For the Humax IRCI 5400 you'll find here a short description:

In order to check the validity of the MPEG Transport stream of our MPEG encoder prototype board we have implemented an LVDS interface to a Humax IRCI 5400 DVB-S settop-box. The demodulated MPEG transport stream connection between the Philips demodulator chip TDA8044 just after the Tuner is disconnected inside the Humax just before it drives the Irdeto CAM chip. Within the Humax this is relative easy because several series resistors on every Transport Stream data and clockline exist on the main board to prevent overvoltage at the output pins of the demodulator chip. The Irdeto CAM chip runs on 5V supply while the TDA8044 supply voltage equals 3.3 V.

Figure 10. Part of schematic of the Humax IRCI5400 which shows the MPEG2 interfacing between demodulator and Irdeto chip

The following description is just to inform you how to make an MPEG2 interface on your Humax IRCI5400. We do not accept any responsibility for any damage caused by the following instructions ! We just describe how we have implemented such an interface on our receiver by our own. If you don't think that you're able to do this job by yourself then leave your Humax original!. At last but not least: warranty void if you apply these changes.

First of all the series resistors have to be removed. Unfortunately these resistors are very small : 0603 types. The resistors between the MPEG TS datalines (8043D0-8043D7 in schematic above) are formed by two resistor packs. If you try to remove these parts then please be very careful not to damage the very fragile PCB tracks to it. In our case the resistor R29 in the schematic wasn't a resistor but a kind of choke. No problem... just look at the pin numbers of the TDA8044 in the schematic and you'll find the correct place on your PCB where you can disconnect the Transport Stream in your STB. After removal of the resistors a special PCB have to be connected between both ends of the disconnected MPEG TS lines on the PCB. The lines coming from the TDA8044 are in fact the MPEG Transport Stream (TS) output lines of the STB receiver and the lines to the Irdeto Chip are in fact our newly created inputs of the MPEG decoder. Because we still want to be able to receive satellite signals with our Humax it is needed to connect some kind of input multiplexer between our disconnected TS lines. We took a little PCB where we placed 3 x DS90LV048A LVDS receiver IC's from National. These IC's are able to convert the differential (LVDS) MPEG TS signals coming from our encoder to single ended logic 3.3 Volt levels. The outputs of these IC's are fed to another 3 x 74CBT3257 2-input multiplexer IC's from Texas Instruments. The control lines of the multiplexer IC's are put together and are connected via a resistor to 3.3V. This control line is also fed to one pin of the DB25 connector where the external MPEG TS will be connected to. This pin will be shorted to ground when the external DB25 MPEG TS connector will be connected with the MPEG encoder board. In that case the multiplexer IC's will automattically route the external MPEG signal to the MPEG decoder input on our Humax main board. If the external MPEG connector is pulled out then the multiplexers route the original TS signal from the internal 8044 demodulator to the internal MPEG decoder again.
For some software reason inside the Humax it is needed to apply a valid satellite signal from a dish to the Humax even if you just want to look at your own injected external MPEG2 signal. This has to due with all kind of internal software checks of the tuner and demodulator which unfortunately seem to be needed to get a valid picture out of it.

Figure 11. Inside view of our MPEG2 interfacing on the Humax IRCI5400

Figure 12. Another view of our MPEG2 interface. Above you see PCB with LVDS receivers and multiplexers

MPEG2 Encoder Prototype :

We have several working MPEG2 encoder prototypes at this moment. See the picture below. This prototype is just used for hardware/software development of our D-ATV modulator project. In a later stadium we will redesign a new (and smaller!) PCB.

Figure 13. Picture of our previous MPEG2 encoder prototype.

Modulator Board Prototype :

For experimenting with our VHDL code in real life we have made a special modulator prototype board. See the picture below.

Figure 14. Early days first development prototype of the digital modulator board.