I think :
The best solution would be adding GND/PWR planes and dropping
vias to GND/PWR planes close to your I/O buffers. But if you can
not add seperate GND/PWR planes and if you donot have area constraint
in your design then above approach of splitting your
single wide line into bunch of lines would be really neat and
moreover you can optimally route those lines so that IO switching
current pathlenght are minimized. BTW the effective inductance
of the single wide strip would be definitely higher than the
bunch of narrow strips ( total width and thicknesses are same )
Hope it helps, regards
Nirmal
>
>This may already have been discussed before on this forum, if so I would
>appreciate any info about this in the archives or if you could send me any
>info by email to me instead of the forum please do so to
>manju%[email protected]
>
>Thank you
>regards
>manju
>
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