Fred Townsend
[email protected]
DC to Light
Consulting Services
[email protected] wrote:
>
> Hello,
>
> I would just like to check with anyone who has done any discrete components
> design
> that uses 500 MHz clock. This translates to a 2ns period and a risetime
> of less than
> 0.5 ns. Does anyone know if this high speed design will work on a normal
> 8 layer
> FR4 board or any suggestions and comments are greatly appreciated. We did
> ran some
> simulation using PNC signal integrity and apparent it did not show very
> optimistic results.
>
> Thanks in advance.
>
> ******************************************************************************
> Cheah Soo Lan
> DSO NATIONAL LAB.
> 20 SCIENCE PARK DRIVE
> SINGAPORE 118 230
>
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