Pin identification

Documentation.
Pin identification, truth tables and shortcuts to make the individual entries as small as possible.

PIN IDENTIFICATION

General:

Missing pins have no pin number.
Unconnected pins and test pins that should be left floating have no identification.
Clock signals are identified by CLK for positive-edge triggering or /CLK for negative-edge triggering.
Reset (clear) inputs are identified by RST.
Set inputs are identified by SET.
For 3-state devices, output enables are indicated by OE.
When a pin has two modes, or selects between two operations, then the two may be separated by a slash. An inversion slash may still be present as in SH//LD for shift or load select.
Pins that have more than one function (selected by programming or the state of another pin) are indicated by both functions separated by a space.

Power supply:

The main power supply is indicated by VCC.
System ground is indicated by GND.
A secondary positive power supply may be indicated by VDD.
A negative power supply is indicated by VEE.
Programming power supply (usually higher than VCC) is indicated by VPP.

Gates, line drivers etc.:

Inputs are identified by letters starting from A.
Outputs are indicated by Y.

Flip-flops:

Inputs are identified by J and K, or D.
Outputs are indicated by Q.

Counters:

Load inputs are indicated by P followed by the counter stage number.
Outputs are indicated by Q followed by the counter stage number. Thus (assuming a binary counter) Q0 is the /2 output, Q1 the /4 output.

Shift registers:

Parallel inputs or bidirectional parallel I/O pins are identified by P followed by the shifter stage number. The leftmost stage in a shift register is number 0.
Serial inputs are identified by letters starting from D (for right shift) or from L (for left shift). If more than one of either is available, the letter is followed by the shifter stage number it feeds.
Serial outputs are identified by Q, which may be followed by the shifter stage number if more than one serial output exists.
Parallel outputs are identified by Q (only if no serial outputs exist), Y (3-state outputs or output latch) followed by the shifter stage number.
Unidirectional shift registers shift towards higher stage numbers.
Bidirectional shift registers have separate shift-left and shift-right serial inputs.
Parallel-in parallel-out shift registers are called univeral.

Multiplexers:

Inputs are identified by A followed by a number.
Outputs are indicated by Y.
Select inputs are identified by S followed by a number starting at 0, unless there is only one select input in which case only S is specified. When the S inputs are taken as a binary number, the value indicates which input is selected.

Demultiplexers:

Inputs are indicated by A, preceded by a section number if more than one.
Outputs are identified by Y followed by a number. When there is more than one multiplexer section, inputs are prefixed by a number indicating to which section they belong.
Select inputs are identified by S followed by a number starting at 0, unless there is only one select input in which only S is specified. When the S inputs are taken as a binary number, the value indicates which output is selected. For noninverting demultiplexers unselected outputs are 0, for inverting demultiplexers they are 1.

Analog multiplexers/demultiplexers:

Analog switches generally are bidirectional, and inputs and outputs can therefore be reversed. One side of the switch is indicated by X (optionally followed by a number), the other side is indicated by Y.
Select inputs are identified by S followed by a number starting at 0, unless there is only one select input in which only S is specified. When the S inputs are taken as a binary number, the value indicates which switch is selected.

Memories:

Address inputs are indicated by A followed by the bit number, starting from 0. Multiport memories use RA or WA for separate read and write addresses, or A prefixed by the port number followed by the bit number.
Data inputs or data I/O are indicated by D followed by a number starting from 0.
Data outputs are indicated by Q followed by a number.

Oscillators:

One-inverter oscillators are indicated by X0 and X1 pins, where X0 is the inverters' output and X1 is the input. If I happen not to know which is which, the pins are indicated by X1 and X2. A crystal oscillator usually requires a crystal parallel to a 10M resistor, with two small capacitors to ground; but sometimes only a crystal is needed -- most often when a 32kHz watch crystal can be used.
Two-inverter oscillators are indicated by X1 (input), X0 (middle node) and X2 (output). A crystal oscillator can then be made using X0 and X1.

Sections:

When a device has several (largely) independent sections, I/O pins are prefixed by the section number, starting from 1, as in 1J or /1Q.
Multi-bit functions, such as counters or 3-state buffers have I/O pins suffixed by the bit number, usually starting from 0 (except sometimes for counters which may have some outputs missing).
The section/bit numbering is used in a different way for (de)multiplexers.

TRUTH TABLES

For inputs, the following notations are used:

   0  : logic low level
   1  : logic high level
   X  : don't care, either 0 or 1
   /  : rising or positive-edge clock input
   \  : falling or negative-edge clock input
   !/ : not a rising edge, either 0, 1 or \
   !\ : not a falling edge, either 0, 1 or /
   .  : 'continued', used in compressing the table

For outputs, the following notations are used:

   0 : logic low level
   1 : logic high level
   Z : high impedance, either 3-state or open-collector not driving output
   - : no change (latched in closed state, or register value not changed)
   ? : undefined (although some manufacturers may define a behaviour)
   . : 'continued', used in compressing the table

ASSUMPTIONS FOR DIGITAL DEVICES

Single/Dual Flip-flops:

The clock is positive-edge triggered.
Complementary outputs are available.

Multiple flip-flops:

Only inverting or noninverting outputs are available.

Synchronous counters:

The clock is positive-edge triggered.
LOAD,SET and RESET are synchronous.

Asynchronous counters:

The clock is negative-edge triggered.
LOAD,SET and RESET are asynchronous.

Shift registers:

The clock is positive-edge triggered.
LOAD and RESET (if available) are synchronous.

ASSUMPTIONS FOR ANALOG DEVICES

Operational amplifiers:

VCC usually is +15V, VEE -15V.
For single/dual-supply op-amps, VEE can be connected to GND.

Analog multiplexers/demultiplexers:

Analog switches generally are bidirectional, and inputs and outputs can therefore be reversed. One side of the switch is indicated by X (optionally followed by a number), the other side is indicated by Y.
Select inputs are identified by S followed by a number starting at 0, unless there is only one select input in which only S is specified. When the S inputs are taken as a binary number, the value indicates which switch is selected.
Select and enable inputs are at TTL level, except for 4000-series CMOS where these inputs must swing between GND and VCC.

Digtal/analog converters:

Select and data inputs are at TTL level.
Current output DACs may have both OUT and inverted /OUT output current pins.