PN2060C Phase Noise Analyzer

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The PN2060C Phase Noise Analyzer measures the amplitude, phase noise of high-performance RF sources.



Independent input and reference frequencies from 1 to 200MHz

No phase-locking or measurement calibration required

Dual reference oscillator inputs allow cross-correlation measurements

Measurement results are saved to file automatically

Scripts are provided for post-data manipulation, raw data (full 4 channels baseband, 32Mbytes/S) can be exported for further analysis

USB3.0 interface with high-speed data exchange

Allan deviation: two channel cross-correlation supported

TCPServer application available: can send data streams to other applications.



Phase noise at offsets from 0.01Hz to 1MHz and levels typically below -185dBc/Hz (10MHz floor)

One high quality USB3.0 cable is enough to complete data collection and power supply


System Noise Floor Specification:



10MHz carrier (90minutes)














Electrical Specifications: Input Signal Level: 10dBm (max), Input Impedance: 50


Mechanical Specifications

Size: 11 x 10 x 4 (cm), Power: USB3.0 power supply with about 1.3A. Operating Temperature: 0-30deg

Unit Weight: 0.5kg.

Front Panel:  SMA RF connector ( DUT1, DUT2, REF1, REF2)

Real Panel: Type-C ( USB3.0 to Type-C cable needed)


Software: 1) WIN7/WIN10/WIN11 64bit supported (test setup, real-time update of phase noise, and collect raw data), scripts for post-process.

Driver: USB3.0 interface


Hardware Version: PN2060C V1.3



Typical measurement examples:

1) Allan Deviation Floor Test: By using an ordinary 10M OCXO (DATUM 2750053-1), AllanDev floor is tested (about 110 minutes). Better results may be possible by using high quality OCXOs.


2)Test result for a 10M OCXO (DATUM 2750013-1): The input level of the DUT1,2 is about 3.5dBm, and the input level of the REF1,2 is about 7dBm.



3)The noise floor test (self-corr) of the PCBA V1.1, where a 10MHz DATUM 2750013-1 is adopted, and a Wenzel AMP is inserted to raise the signal level to about 10dBm at four input ports. The noise floor is approaching to the theoretical value of -187dBc, i.e., -174dBm-3dB-10dBm=-187dBc with a running time of 90 minutes. The spurs can be optimized with a high-quality external clock and the left ones can be removed by algorithms as detail described in 4). Note: The device is connected to the USB3.0 interface in the back panel of a PC, not the one in the front panel. The USB3.0 in the front panel usually has a long line connected to the motherboard with exposed connectors, which can introduce additional noises and degenerate the noise floor.





4) Analysis for the spurs.

Methods for dealing with spurs: a) choose a sampling frequency which generates spurs as little as possible for a specific frequency of the DUT. b) remove the left ones through algorithms.

V6.06 released:

1) “spur removal” function added;

2) "Four Channel" option added, where all data streams of the 4 channels can be uploaded simultaneously, and processed by the host-PC in real-time (about 32Mbytes/S), and the data streams can be saved for post-analysis also.

3) Real-time precise counter available on the UI: the frequencies of DUT & REF2 can be precisely calculated and display on the UI, based on REF1, i.e., if the frequency of the REF1 is accuracy enough, the frequency of DUT and REF2 displayed on the UI will be accuracy also. It is a very high quality frequency counter, even better than a Keysight 53230a.



5) Demonstration of “Raw Data”: With the “four channel” option, all the information (phase noise, AllanDev, frequencies, etc.) can be extracted from the “Raw Data”, following is an example, where DUT, REF1, REF2 are all 10MHz. New algorithms (or applications) can be developed based on the “Raw Data”.




6) Hardware V1.2 Available: External clock can be supported in an elegant way without any modification.



7) V6.16 released. A TCPServer (with a better algorithm) is implemented in this release. The TCPServer function can send data stream to other applications (Example setup: AllanDEV, tap: 2, sample rate: 2078 sps (Fast) or 1039 sps (Slow), data stream: phase difference of DUT1 to REF1 )




8) By using some high-quality crystals (10M, Q is about 1291K), a 10M OCXO (the output level of which can be adjusted) is designed and verified. Better results can be achieved by changing the capacitors (inductors, resistors) to the high-quality ones (polystyrene capacitors).






9) Phase-locked Module Design

A phase-locked module is designed, where a CVHD-950X-125 is phase-locked to an old OCXO (CTI 10MHz). It can also be locked to a 100MHz (or 200MHz) VCXO (or OCXO).




10) Extreme Test: Direct measurement of a 1GHz DRO

A CCSO-914X3-1000 (CCSO-914X-1000 with a better performance) is measured directly. The input signal is attenuated about 25dB by the front-end of the device in this scenario. It is definitely far beyond the specification of the device, and the noise floor is limited to about -145dBc. However, the measurement result is accurate within 10KHz. Similar measurements are performed in [6], where the DUT is a CVCSO-914-1000, which is a voltage-controlled version.










Ordering Information:


PN2060C V1.3 available

$849USD free shipping worldwide, PayPal accepted, contact us for detail.













1)The current is about 1.1-1.5A totally, which can vary with the frequency of the system’s clock. The USB3.0 of some PCs can not provide such a high current while some of them work normally. Some USB3.0 cards can be helpful. The following types of USB3.0 cards have been fully tested and verified.

Update for some mainboards: the economical one (MSI H610 Series) cannot work properly, MSI B760M is verified and running without problems.



2)The default clock is the internal one, with a fixed frequency of 133MHz, which can help you to verify the performance quickly. When you are familiar with this device, you can try to use an external high-quality clock. Some modifications (minor) are necessary when changing the system’s clock. Simulation results show that the following frequencies are “good” ones for a DUT of 10MHz: 13x.2MHz, 13x.4MHz, 13x.6MHz, 13x.8MHz, where “x” can be any value. These frequencies of the ADC clock generate little spurs when the frequency of the DUT or SYS_CLK is drifted. Then, it is easier to be removed by the algorithm. Method of switching to an external clock for V1.1: remove two capacitors as shown in the following figure. On the UI, select “CLK OUT”, the power supply of the internal clocks will be switched off. It is only for experiment, if handled improperly, damage maybe occurred.


3) A fan is installed internally. It can be removed to avoid noise and potential magnetic coupling between the fan and the rf transformers (many of them onboards). As the fan is running with a speed about 6000rpm (or about 100Hz), some spurs (100Hz, 200Hz, 300Hz, 400Hz, 500Hz, and etc.) maybe visible. And it is very interesting that the magnitude of these spurs can vary from one fan to another one as the magnetic distribution of a fan is different also. In other word, it can be used to detect how circular of the magnetic distribution of a fan.


4) The device should be connected to the USB3.0 interface in the back-panel of a PC, not the one in the front panel. The USB3.0 in the front panel usually has a long line connected to the motherboard with exposed connectors, where additional noises may be introduced and the noise floor may be degenerated also.


5)If the sampling frequency of the ADC is lower, the system’s noise floor may tend to be raised also, especially when the frequency of the DUT is high (e.g., 100MHz). It may be the ADC’s characteristics.


6)For the PN2060C V1.1, more filtering elements are added in the front-end of the ADCs. So, additional losses are induced.


7)The second-Nyquist zone and beyond: When diving into deep water area, all the phenomena reported in [1]-[3] can be encountered with different value of attenuators and with different bandwidth of filters. And aliasing may bring errors in noise floor measurements. An active power splitter is designed to perform some experiments. Test results shown that artifacts are more easily occurred with this active power-splitter.


8) Be careful of the phase difference between DUT1 & DUT2. According to [4], artifacts will be introduced with these differences. These kinds of artifacts are theoretically existed in the digital phase noise analyzer. FSWP utilizes another architecture which is trying to minimize them [5, p18].


9) Make a reliable connection between the type-C connector and the device. Always check the validity of the driver in “device manager”. Try to make a 180-degree rotation if necessary.


10) The measurement result of the noise floor tends to be raised-up in second-Nyquist and beyond according to [14], dual-channel down-converter can be adopted to eliminate this effect.


11) According to [6], dual channel down-converter can be designed. A frequency divider with a very good performance [11] is available in literature, and it may be used in this architecture. VK4ZXI (Drew Wollin) managed to make a measurement with his own setup [13].




I would like to thank for Andrew Holme. In the very beginning of the development of the PNA, I have learned a lot from Andrew’s wonderful work [7] and also asked for some helps. In the process of my design, I have gradually developed my own codes from PN2060A to PN2060C. But still use part of Andrew’s source codes in current release. Andrew has granted permission for me to use his source codes. I would thanks to Jim Henderson, Pual Hsieh, and Drew Wollin for their valuable feedbacks and discussions, where Jim Henderson implemented a mixer-based down-converter to extend the frequency range. Drew Wollin has written an introduction and review for beginners [8]. Pual Hsieh has some valuable discussions with me for potential improvement. I am also would like to thanks IW3AUT for the file converter tool which makes it compatible with other applications [9].



Further reading about phase noise analyzer:

The principle and algorithm of the four-channel digital phase noise analyzer is detailed described in literature about 20 years ago [10]. Following figures [10] describe the detailed process of the four-channel. Firstly, the four channels are DDC (Digital Down Converted) to baseband (I,Q), and then, converted to amplitude and phase through a standard CORDIC algorithm. At last, all the data are uploaded to a PC, and processed according to these figures. There are a lot of such platforms available on market. I just build such a platform which I was preferred as no one such platform satisfy my requirement.

Anyone who is interested in phase noise measurement can dig deep into [12], where full of the most important materials in this area.






[1] Y. Gruson, A. Rus, U. L. Rohde, A. Roth, and E. Rubiola, “Artifacts and errors in cross-spectrum phase noise measurements,” Metrologia, vol. 57, no. 5, pp. Art. no. 055 010 p. 1–12, Oct. 2020, open access.

[2] Y. Gruson, V. Giordano, U. L. Rohde, A. K. Poddar and E. Rubiola, "Cross-spectrum PM noise measurement thermal energy and metamaterial filters", IEEE Trans. Ultrason. Ferroelectr. Freq. Control, vol. 64, no. 3, pp. 634-642, Mar. 2017.

[3] Nelson CW, Hati A, Howe DA. “A collapse of the cross-spectral function in phase noise metrology”. Rev Sci Instrum. 2014 Feb;85(2):024705.

[4] Nelson, C.W., Hati, A. and Howe, D.A. (2013), Phase inversion and collapse of cross-spectral function. Electron. Lett., 49: 1640-1641.


[6] MicroChip. UHF and Microwave Measurements with the 53100A Phase Noise Analyzer(AN3899).

[7] Andrew Holme.

[8] Drew Wollin.

[9] IW3AUT.

[10] Grove, J. et al., "Direct-digital phase-noise measurement," Proc. of 2004 IEEE International Frequency Control Symposium, Montreal, Canada, pp. 287-291, August 2004.

[11] M. M. Driscoll, "Phase noise performance of analog frequency dividers," in IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, vol. 37, no. 4, pp. 295-301, July 1990, doi: 10.1109/58.56490.